INTEL DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartus-24.3.1-1.14-readme.txt Readme file for Intel(R) Quartus(R) Prime 24.3.1 Patch 1.14 Copyright (C) Intel Corporation 2019 All right reserved. Patch created on March 27, 2025, 9:46 p.m. Patch Case#: 14024333140 Patches included: Patches conflicted: Patch prerequisites: //**************************************************************** Description: Patch# 1.14: Modify altera_s10_configuration_clock.sdc to constrain altera_int_osc_clk properly in the Configuration Clock Intel FPGA IP core. The erroneous constraint prevented Quartus from identifying the correct clock node in the design and subsequently led to erroneous timing closure results. Caution - You must either have previously installed the Intel(R) Quartus(R) Prime 24.3.1 software or must install the Intel(R) Quartus(R) Prime 24.3.1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Intel(R) Quartus(R) Prime software will not run properly. Note: <Patches included> - means this patch includes those patches. If you already installed those patches, you can safely install this new patch on top. <Patches conflicted> - means this patch conflicts with those patches. If you have any of those patches installed, don't install this patch. Contact Intel for further support.