Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 1/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Design Example in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.3. Simulating the Design Example x
1.3.1. Simulation Design Example Components
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Compile the Design Example in Hardware 1.4.2. Configure the Clocks in Hardware 1.4.3. Program the FPGA
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.3.1
IP Version 5.0.0

The Agilex™ 5 Low Latency 40G Ethernet Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the Quartus® Prime IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

The Intel® FPGA IP also includes a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Design Example

Section Content
Generating the Design Example
Directory Structure
Simulating the Design Example
Compiling and Configuring the Design Example in Hardware
Testing the Design Example in Hardware

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