DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

ID 823560
Date 12/20/2024
Public
Document Table of Contents

1.4. Simulating the Design

The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
Note: The testbench only supports 4 lanes of TX and 4 lanes of RX for simulation.
  1. Navigate to the simulation folder of your choice.
  2. Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    A successful simulation ends with Source and Sink SRC comparison, as shown below:
    # SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
    # SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
    # Pass: Test Completed
    Table 1.  Steps to Run Simulation
    Simulator Working Directory Instructions
    QuestaSim* /simulation/mentor
    In the command line, type
    vsim -c -do mentor.do
    Xcelium* /simulation/xcelium
    In the command line, type
    source xcelium.sh
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type
    source vcsmx_sim.sh