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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode
1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
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1.4. Simulating the Design
The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
Note: The testbench only supports 4 lanes of TX and 4 lanes of RX for simulation.
- Navigate to the simulation folder of your choice.
- Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
- Analyze the results.
A successful simulation ends with Source and Sink SRC comparison, as shown below:
# SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c, # SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c, # Pass: Test Completed
Table 1. Steps to Run Simulation Simulator Working Directory Instructions QuestaSim* /simulation/mentor In the command line, typevsim -c -do mentor.do
Xcelium* /simulation/xcelium In the command line, typesource xcelium.sh
VCS* MX /simulation/synopsys/vcsmx In the command line, typesource vcsmx_sim.sh