DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. Design Example: DisplayPort SST Parallel Loopback without PCR 4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface 5. Design Example: DisplayPort SST TX-Only Design 6. Design Example: DisplayPort SST RX-Only Design 7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating ELF File 1.7. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Design Components 2.2. Clocking Scheme 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. Design Example: DisplayPort SST Parallel Loopback without PCR x
3.1. Features 3.2. Functional Description 3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode 3.4. DisplayPort SST Parallel Loopback without PCR with Dual-Simplex Mode 3.5. GTS DisplayPort PHY Dual Simplex Mode IP Generation Flow
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface x
4.1. Features 4.2. Functional Description
5. Design Example: DisplayPort SST TX-Only Design x
5.1. Features 5.2. Functional Description
6. Design Example: DisplayPort SST RX-Only Design x
6.1. Features 6.2. Functional Description
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

2.4. Simulation Testbench

The simulation testbench simulates the DisplayPort TX serial loopback to RX.
Figure 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
Table 13.  Testbench Components
Component Description
Video Pattern Generator This generator produces color bar patterns that you can configure. You can parameterize the video format timing.
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX core. The testbench control block also reads the CRC value from both source and sink to make comparisons.
RX Link Speed Clock Frequency Checker This checker verifies if the RX transceiver recovered clock frequency matches the desired data rate.
TX Link Speed Clock Frequency Checker This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate.

The simulation testbench does the following verifications:

Table 14.  Testbench Verifications
Test Criteria Verification
  • Link Training at Data Rate HBR3
  • Read the DPCD registers to check if the DP Status sets and measures both TX and RX Link Speed frequency.
 Integrates Frequency Checker to measure the Link Speed clock's frequency output from the TX and RX transceiver.
  • Run video pattern from TX to RX.
  • Verify the CRC for both source and sink to check if they match
  • Connects video pattern generator to the DisplayPort Source to generate the video pattern.
  • Testbench control next reads out both Source and Sink CRC from DPTX and DPRX registers and compares to ensure both CRC values are identical.
Note: To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
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