AN 307: Intel® FPGA Design Flow for Xilinx* Users

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ID 683562
日付 3/20/2018
Public
ドキュメント目次
ドキュメント目次 x
1. Introduction to Intel® FPGA Design Flow for Xilinx* Users 2. Technology Comparison 3. FPGA Tools Comparison 4. Xilinx* to Intel® FPGA Design Conversion 5. Conclusion 6. Document Revision History for Intel® FPGA Design Flow for Xilinx* Users
2. Technology Comparison x
2.1. Intel® FPGAs 2.2. Xilinx* FPGAs 2.3. Comparison Table 2.4. Intel® FPGA Device Features
3. FPGA Tools Comparison x
3.1. Hardware and Software Tools for FPGA Design 3.2. FPGA Design Flow Using Command Line Scripting 3.3. FPGA Design Flow Using Tools with GUIs 3.4. Additional インテル® Quartus® Primeプロ・エディション Features
3.2. FPGA Design Flow Using Command Line Scripting x
3.2.1. Command-Line Executable Equivalents 3.2.2. Programming and Configuration File Support in the インテル® Quartus® Primeプロ・エディション Software
3.2.1. Command-Line Executable Equivalents x
3.2.1.1. synth_design 3.2.1.2. place_design/route_design 3.2.1.3. report_timing 3.2.1.4. write_bitstream 3.2.1.5. write_sdf/write_verilog/write_vhdl 3.2.1.6. report_power 3.2.1.7. write_checkpoint 3.2.1.8. Run Complete Design Flow
3.3. FPGA Design Flow Using Tools with GUIs x
3.3.1. Project Creation 3.3.2. Design Entry 3.3.3. IP Status 3.3.4. Design Constraints 3.3.5. Synthesis 3.3.6. Design Implementation 3.3.7. Finalize Pinout 3.3.8. Viewing and Editing Design Placement 3.3.9. Static Timing Analysis 3.3.10. Generation of Device Programming Files 3.3.11. Power Analysis 3.3.12. Simulation 3.3.13. Hardware Verification 3.3.14. View Netlist 3.3.15. Design Optimization 3.3.16. Techniques to Improve Productivity 3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
3.3.2. Design Entry x
3.3.2.1. HDL Editor 3.3.2.2. Schematic/Block Editor 3.3.2.3. State Machine Editor 3.3.2.4. IP Catalog and Parameter Editor 3.3.2.5. プラットフォーム・デザイナー System Integration Tool 3.3.2.6. Platform Designer Component Editor
3.3.4. Design Constraints x
3.3.4.1. Assignment Editor 3.3.4.2. Create Timing Constraints with the タイミング・アナライザー GUI 3.3.4.3. Create Timing Constraints with the タイミング・アナライザー Text Editor
3.3.7. Finalize Pinout x
3.3.7.1. Pin Planner 3.3.7.2. インターフェイス・プランナー
3.3.12. Simulation x
3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores
3.3.13. Hardware Verification x
3.3.13.1. System Console 3.3.13.2. Signal Tap Logic Analyzer 3.3.13.3. In-System Sources and Probes 3.3.13.4. Transceiver Toolkit 3.3.13.5. EMIF Debug Toolkit 3.3.13.6. リモートデバッグ 3.3.13.7. その他の Intel® FPGAデバッグツール
3.3.14. View Netlist x
3.3.14.1. RTL Viewer 3.3.14.2. Technology Map Viewer
3.3.15. Design Optimization x
3.3.15.1. Hyper-Aware Design Flow 3.3.15.2. Physical Synthesis Optimization
3.3.16. Techniques to Improve Productivity x
3.3.16.1. Rapid Recompile 3.3.16.2. Block-Based Design Flow 3.3.16.3. Design Space Explorer II
3.4. Additional インテル® Quartus® Primeプロ・エディション Features x
3.4.1. Scripting with Tcl in the インテル® Quartus® Primeプロ・エディション Software
3.4.1. Scripting with Tcl in the インテル® Quartus® Primeプロ・エディション Software x
3.4.1.1. Running Scripts from the DOS or UNIX Prompt 3.4.1.2. Running Scripts in Batch Mode from a Shell 3.4.1.3. Running Tcl Commands Directly from the Command Line 3.4.1.4. Running Tcl Commands Interactively from the Shell 3.4.1.5. The インテル® Quartus® Prime Tcl Console Window
4. Xilinx* to Intel® FPGA Design Conversion x
4.1. Replacing Xilinx* Primitives 4.2. Converting IP Cores 4.3. Setting Equivalent Xilinx* Design Constraints 4.4. Setting Up the Simulation Environment
4.1. Replacing Xilinx* Primitives x
4.1.1. Converting I/O Buffers 4.1.2. Changing Default I/O Standard for Pins
4.1.1. Converting I/O Buffers x
4.1.1.1. Example of Converting I/O Buffer
4.2. Converting IP Cores x
4.2.1. Converting Memory Blocks 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) 4.2.3. Converting Multipliers
4.2.1. Converting Memory Blocks x
4.2.1.1. Embedded Memory Blocks 4.2.1.2. Differences Between Xilinx* Memory and Intel® FPGA Memory 4.2.1.3. Determining Memory Block and Mapping Ports 4.2.1.4. Memory Port Mapping 4.2.1.5. Example: Converting Simple Dual-Port RAM
4.2.1.2. Differences Between Xilinx* Memory and Intel® FPGA Memory x
4.2.1.2.1. Memory Mode 4.2.1.2.2. Clocking Mode 4.2.1.2.3. Write and Read Operation Triggering 4.2.1.2.4. Read-During-Write Operation at the Same Address 4.2.1.2.5. Error Correction Code (ECC) 4.2.1.2.6. Byte Enable 4.2.1.2.7. Address Clock Enable 4.2.1.2.8. Parity Bit Support 4.2.1.2.9. Memory Initialization 4.2.1.2.10. Output Synchronous Set/Reset
4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) x
4.2.2.1. Feature Comparison 4.2.2.2. Port Mapping Reference 4.2.2.3. Example: Converting Xilinx* MMCM into an Intel® PLL
4.2.3. Converting Multipliers x
4.2.3.1. Feature Comparison 4.2.3.2. Port Mapping 4.2.3.3. Example: Converting to the LPM_MULT IP Core 4.2.3.4. Example: Converting to the Intel® FPGA Multiply Adder IP core
4.3. Setting Equivalent Xilinx* Design Constraints x
4.3.1. Device Constraints 4.3.2. Placement Constraints 4.3.3. Timing Constraints 4.3.4. Retimer Constraints
4.3.1. Device Constraints x
4.3.1.1. DRIVE 4.3.1.2. SLEW 4.3.1.3. IOB 4.3.1.4. IOSTANDARD 4.3.1.5. KEEP
4.3.2. Placement Constraints x
4.3.2.1. PBLOCK 4.3.2.2. PACKAGE_PIN 4.3.2.3. LOC & BEL 4.3.2.4. PROHIBIT
4.3.2.1. PBLOCK x
4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions
4.3.3. Timing Constraints x
4.3.3.1. set_clock_groups
4.4. Setting Up the Simulation Environment x
4.4.1. Simulation Levels 4.4.2. HDL Support for EDA Simulators 4.4.3. Value Change Dump (VCD) Support 4.4.4. Simulating Intel FPGA IP Cores
1. Introduction to Intel® FPGA Design Flow for Xilinx* Users
2. Technology Comparison
3. FPGA Tools Comparison
4. Xilinx* to Intel® FPGA Design Conversion
5. Conclusion
6. Document Revision History for Intel® FPGA Design Flow for Xilinx* Users

4.2.3.3. Example: Converting to the LPM_MULT IP Core

You can convert the Xilinx* Multiplier Core that targets a Xilinx* device into multipliers for an Intel® FPGA device by using the IP Catalog.
In this example, the test module instantiates the mymult module, created using the Xilinx* Core Generator. The parameters are:
表 55.  Parameters of Multiplier Module
Parameter Value
Multiplier Type Parallel multiplier where neither of the on the input buses is a constan value
Input data width 18 bits
Input data type Signed
Output result width Restricted to 36 bits
Number o pipeline stages 2
Implemented using Multipliers and optimized for Speed
The Original Verilog HDL Code in the Vivado* Software is: 
module top(
        input clk,
        input [17:0] a,
        input [17:0] b,
        input ce,
        input sclr,
        output [35:0] p
        );
mymult i1 (
    .CLK(clk),
    .A(a), // Bus [17: 0]
    .B(b), // Bus [17: 0]
    .CE(ce),
    .SCLR(sclr),
    .P(p)); // Bus [35: 0]
endmodule
The original VHDL Code in the Vivado* Software is: 
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY work;

ENTITY test IS
port (
        clk: IN STD_LOGIC;
        a: IN STD_LOGIC_VECTOR(17 downto 0);
        b: IN STD_LOGIC_VECTOR(17 downto 0);
        sclr: IN STD_LOGIC;
        ce: IN STD_LOGIC;
        p: OUT STD_LOGIC_VECTOR(35 downto 0)
        );
END test;

ARCHITECTURE arch OF test IS 

component mymult
        PORT(
            CLK: IN STD_LOGIC;
            A: IN STD_LOGIC_VECTOR(17 downto 0);
            B: IN STD_LOGIC_VECTOR(17 downto 0);
            CE: IN STD_LOGIC;
            SCLR: IN STD_LOGIC;
            P: OUT STD_LOGIC_VECTOR(35 downto 0)
            );
end component;

BEGIN
i1: mymult
PORT MAP(CLK => clk,
A => a, B => b, CE => ce,
SCLR => sclr, P => p);
END;
In the IP Catalog, select the LPM_MULT IP core to create the equivalent mymult module.
Converted Verilog HDL Code in the インテル® Quartus® Primeプロ・エディション software: 
module test(
            input clk,
            input [17:0] a,
            input [17:0] b,
            input ce,
            input sclr,
            output [35:0] p
            );
mymult i1 (
        .clock(clk),
        .dataa(a), // Bus [17: 0]
        .datab(b), // Bus [17: 0]
        .clken(ce),
        .sclr(sclr),
        .result(p)); // Bus [35: 0]
endmodule
Converted VHDL Code in the インテル® Quartus® Primeプロ・エディション Software 
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY test IS
        port (
            clk: IN STD_LOGIC;   
            a: IN STD_LOGIC_VECTOR(17 downto 0);
            b: IN STD_LOGIC_VECTOR(17 downto 0);
            ce: IN STD_LOGIC;
            sclr: IN STD_LOGIC;
            p: OUT STD_LOGIC_VECTOR(35 downto 0)
            );
END test;

ARCHITECTURE arch OF test IS

component mymult
    PORT(clock: IN STD_LOGIC;
        dataa: IN STD_LOGIC_VECTOR(17 downto 0);
        datab: IN STD_LOGIC_VECTOR(17 downto 0);
        clken: IN STD_LOGIC;
        sclr: IN STD_LOGIC;
        result: OUT STD_LOGIC_VECTOR(35 downto 0)
    );
end component;

BEGIN
i1: mymult
PORT MAP(clock => clk,
        dataa => a,
        datab => b,
        clken => ce,
        sclr => sclr,
        result => p);
END;
レベル 2 の表題