Advanced Logic Synthesis for Electronics (“A.L.S.E”), offers an exhaustive range of IPs, Design Services, Trainings and Boards to help you with the design of FPGA-based applications, ASICs, or Embedded Systems.
オファリング
提供内容
The new HyperRAM memories, based on low-power PSRAM technology, are very welcome addition to the traditional RAM memories portfolio. They provide good bandwidth performance while using a limited amount of pins. The interface known as « HyperBus » offers a low signal count (typically 12 pins). The memories offer a Low Power consumption, Hidden Refresh, and Automotive temperature ranges. These memories are optimized for Mobile and Automotive applications. Typical power consumption during burst read is about 60mA. ALSE has then designed an extremely efficient HyperRam Memory Controller, in order to provide an easy interface to the HyperRAM memories, along with very high performance and efficiency and a lot of advantages when compared to other controllers.
提供内容
This JPEG Baseline Encoder IP has been designed for easy integration into all kinds of FPGAs. It has been highly optimized for a very small footprint and an excellent Fmax, enabling the use of low cost FPGAs.This IP can compress Still Images and Video Streams and it comes with Raster-to-Block conversion integrated. Several popular input formats are supported natively (BT656, YUV, RGB), thus simplifying the connection to various image sensors or video streaming sources (Video Codecs, Ethernet streams etc). Deliverables include a very sophisticated HDL simulation environment for seamless development, verification and integration in the final application. Since 2012, this IP has been used in a lot of projects and FPGAs.For higher resolutions and frame rates, we have developed in 2024 a High-Speed version of this Encoder.
提供内容
This new High-Speed JPEG-Encoder IP is an augmented variation of our standard JPEG encoder. It has been designed for a nearly doubled performance, allowing to encode in real time a higher resolution than Full-HD (1920x1080) at 60 fps while using low cost and small FPGAs. Its still small footprint, no external memory, good quality, and efficient compression makes it an ideal choice for a lot of use cases.This JPEG-Encoder IP can compress Still Images and Video Streams and it comes with Raster-to-Block conversion option integrated. Several popular input formats are supported natively (BT656, YUV, RGB), thus simplifying the connection to various image sensors or video streaming sources (Video Codecs, Ethernet streams etc). Deliverables include a very sophisticated HDL simulation environment for seamless development, verification and integration in the final application.Coupled with our GEDEK Ethernet IP and RTP framer, it makes a perfect solution for video streaming over Ethernet.
提供内容
JESD204B is a standard that provides the ability to transfer reliably Data at very high speeds between an FPGA and an ADC (JESD204B - Rx) or a DAC (JESD204B - Tx). It is based on the use of transceivers to transmit & receive serially at very high speed parallel Data on one or several lanes. This is the PHY layer, based on the Transceivers available on the FPGA you are using. The Link layer is the protocol (8B/10B for JESD204B including scrambling, encoding, character and lanes alignments, assembling…)The transport layer deals with frames of data. And in practice, a control & status registers interface is available to monitor and control the IP.
提供内容
Quad-SPI Flash memories have many advantages : high speed, low pin count, small packages, and low cost ! ALSE Quad-SPI Flash Controller IP has been designed for ultimate performance, small footprint and easy integration in all kinds of FPGAs, low-cost to high-end. Dramatically reduce the boot time, store streaming video, or even run processor code directly from the Flash, etc. The unique CFI Emulation (optional) feature further facilitates the adoption of Serial Flash memories. Supports all types of Quad SPI Flash Memories. Deliveries include a HDL simulation environment for seamless integration in any project. Our Quad-SPI controller has been used successfully by many customers in different contexts, always delivering outstanding performance.
提供内容
The Aurora 8B/10B IP Core is a data transfer IP based on a lightweight and open protocol. It is suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers. This IP targets Intel® / Altera FPGA devices and is compatible with the public Aurora 8B/10B protocol. The Aurora protocol enables Intel FPGA to interconnect with other FPGAs, ASICs or ASSPs supporting the standard Aurora protocol.It is fully compatible and interoperable with the Xilinx/AMD Aurora 8B/10B IP.
提供内容
GEDEK is the easiest and best performance solution to exchange data reliably over Ethernet. It is a hardware solution, very compact, that does not require any processor nor embedded software while offering 100% bandwidth. Available for 100M, 1G, Triple speed Eth. A 10G version is also available.
提供内容
Aurora 64B/66B is a multi-lane lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers (6 to 28 GB/s per lane, so up to more than 400G ). The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of this protocol offering full compatibility and interoperability.
提供内容
In 2024, ALSE launches an FPGA IP for AVB Milan, thus allowing any company in the Professional Audio field to develop products incorporating the MILAN technology and protocols in record time, with very low effort, and guaranteed performance and compliance.